#define UART_WORD_LEN_5     (0) /*!< UART_LINE setting to set UART word length to 5 bits */
#define UART_WORD_LEN_6     (1) /*!< UART_LINE setting to set UART word length to 6 bits */
#define UART_WORD_LEN_7     (2) /*!< UART_LINE setting to set UART word length to 7 bits */
#define UART_WORD_LEN_8     (3) /*!< UART_LINE setting to set UART word length to 8 bits */

#define UART_PARITY_NONE    (0x0 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as no parity   */
#define UART_PARITY_ODD     (0x1 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as odd parity  */
#define UART_PARITY_EVEN    (0x3 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as even parity */
#define UART_PARITY_MARK    (0x5 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '1'  */
#define UART_PARITY_SPACE   (0x7 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '0'  */

#define UART_STOP_BIT_1     (0x0 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for one stop bit  */
#define UART_STOP_BIT_1_5   (0x1 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for 1.5 stop bit when 5-bit word length  */
#define UART_STOP_BIT_2     (0x1 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for two stop bit when 6, 7, 8-bit word length */

#define UART_FIFO_RFITL_1BYTE        (0x0 << UART_FIFO_RFITL_Pos)   /*!< UART_FIFO setting to set RX FIFO Trigger Level to 1 bit */
#define UART_FIFO_RFITL_4BYTES       (0x1 << UART_FIFO_RFITL_Pos)   /*!< UART_FIFO setting to set RX FIFO Trigger Level to 4 bits */
#define UART_FIFO_RFITL_8BYTES       (0x2 << UART_FIFO_RFITL_Pos)   /*!< UART_FIFO setting to set RX FIFO Trigger Level to 8 bits */
#define UART_FIFO_RFITL_14BYTES      (0x3 << UART_FIFO_RFITL_Pos)   /*!< UART_FIFO setting to set RX FIFO Trigger Level to 14 bits */

#define UART_FIFO_RTSTRGLV_1BYTE     (0x0 << UART_FIFO_RTSTRGLV_Pos)  /*!< UART_FIFO setting to set RTS Trigger Level to 1 bit */
#define UART_FIFO_RTSTRGLV_4BYTES    (0x1 << UART_FIFO_RTSTRGLV_Pos)  /*!< UART_FIFO setting to set RTS Trigger Level to 4 bits */
#define UART_FIFO_RTSTRGLV_8BYTES    (0x2 << UART_FIFO_RTSTRGLV_Pos)  /*!< UART_FIFO setting to set RTS Trigger Level to 8 bits */
#define UART_FIFO_RTSTRGLV_14BYTES   (0x3 << UART_FIFO_RTSTRGLV_Pos)  /*!< UART_FIFO setting to set RTS Trigger Level to 14 bits */

#define UART_IS_RX_READY(uart)		((uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) >> UART_FIFOSTS_RXEMPTY_Pos)
#define UART_IS_TX_EMPTY(uart)		((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)
#define UART_IS_TX_FIFO_FULL(uart)	((uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) >> UART_FIFOSTS_TXFULL_Pos)

vsf_err_t m45x_usart_init(uint8_t index);
vsf_err_t m45x_usart_fini(uint8_t index);
vsf_err_t m45x_usart_config(uint8_t index, uint32_t baudrate,
								uint8_t datalength, uint8_t mode);
vsf_err_t m45x_usart_config_callback(uint8_t index, void *p,
						void (*ontx)(void *), void (*onrx)(void *, uint16_t));
vsf_err_t m45x_usart_tx(uint8_t index, uint16_t data);
vsf_err_t m45x_usart_tx_isready(uint8_t index);
uint16_t m45x_usart_rx(uint8_t index);
vsf_err_t m45x_usart_rx_isready(uint8_t index);
vsf_err_t m45x_usart_tx_bytes(uint8_t index, uint8_t *data, uint16_t size);
uint16_t m45x_usart_tx_get_avail_length(uint8_t index);
uint16_t m45x_usart_rx_bytes(uint8_t index, uint8_t *data, uint16_t size);
uint16_t m45x_usart_rx_get_data_length(uint8_t index);

